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copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is66wv51216dall is66/67wv51216dbll integrated silicon solution, inc. www.issi.com 1 rev.? a 06/28/2011 8mb? low? voltage, ? ultra ? low? power?pseudo?cmos? static?ram ?? ?????? ????? features ? high-speed access time: C 70ns (is66wv51216dall, is66/67wv51216dbll) C 55ns (is66/67wv51216dbll) ? cmos low power operation ? single power supply C v dd = 1.7v-1.95v (is66wv51216d all) C v dd = 2.5v-3.6v (is66/67wv51216dbll) ? three state outputs ? data control for upper and lower bytes ? industrial temperature available ? lead-free available description the issi is66wv51216dall and is66/67wv51216dbll are high-speed, 8m bit static rams organized as 512k words by 16 bits. it is fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low , cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte (lb) access. the is66wv51216dall and is66/67wv51216dbll are packaged in the jedec standard 48-ball mini bga (6mm x 8mm) and 44-pin tsop (type ii) . the device is aslo available for die sales. functional?block? diagram july ?2011 a0-a18 cs1 oe we 512k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb cs2
2 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll pin? configurations: 48-ball?mini?bga?(6mm?x?8mm) pin?descriptions a0-a18 address inputs i/o0-i/o15 data inputs/outputs cs1, cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 v dd` v dd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 a18 a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 a18 a8 a9 a10 a11 a17 44-pin? tsop? (type?ii)
integrated silicon solution, inc. www.issi.com 3 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll truth ? table ? ? ? ? ? ? ? i/o?pin ? mode? we? cs1? cs2? oe? lb ub? i/o0-i/o7? i/o8-i/o15? v dd ?current? ? not selected x h x x x x high-z high-z i sb 1 , i sb 2 x x l x x x high-z high-z i sb 1 , i sb 2 x x x x h h high-z high-z i sb 1 , i sb 2 output disabled h l h h l x high-z high-z i cc h l h h x l high-z high-z i cc read h l h l l h d out high-z i cc h l h l h l high-z d out h l h l l l d out d out write l l h x l h d in high-z i cc l l h x h l high-z d in l l h x l l d in d in operating ?range?(v dd ) ? ? ? is66wv51216dall ? is66wv51216dbll? is67wv51216dbll? ? range ? ambient? temperature ? (70ns)? (55ns, ?70ns)? (55ns, ?70ns) ? industrial C40c to +85c 1.7v - 1.95v 2.5v - 3.6v C ? automotive, a1 C40c to +85c C C 2.5v - 3.6v automotive, a2 C40c to +105c C C 2.5v - 3.6v note: cs2 input signal pin is only available for 48-ball mini bga package parts. cs2 input is internally enabled for 44-pin tsop-ii pack - age parts. p ower-up?initializ ation is66wv512616dall/dbll and is67wv512616dbll include an on-chip voltage sensor used to launch the power-up initialization process. when vdd reaches a stable level at or above the vdd (min) , the device will require 50s to complete its self-initialization process. during the initialization period, cs should remain high. when initialization is complete, the device is ready for normal operation. 50us vdd vdd (min) 0v device initialization device for normal operation
4 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll dc?electrical? characteristics (over operating range) v dd ?=? 2.5v-3.6v ? symbol? parameter ? test ?conditions? v dd ? min. ? max. ? unit ? v oh output high voltage i oh = -1 ma 2.5-3.6v 2.2 v v ol output low voltage i ol = 2.1 ma 2.5-3.6v 0.4 v v ih input high voltage (1) 2.5-3.6v 2.2 v dd + 0.3 v v il input low voltage (1) 2.5-3.6v C0.2 0.6 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a notes: 1. v ill (min.) = C2.0v ac (pulse width < 10ns). not 100% tested. v ihh (max.) = v dd + 2.0v ac (pulse width < 10ns). not 100% tested. absolute?maximum? ratings (1) ? symbol? parameter ? value ? unit ? v term terminal voltage with respect to gnd C0.2 to v dd +0.3 v t bias temperature under bias C40 to +85 c v dd v dd related to gnd C0.2 to +3.8 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rat - ing conditions for extended periods may affect reliability. dc?electrical? characteristics (over operating range) v dd ?=? 1.7v-1.95v ? symbol? parameter ? test ?conditions? v dd ? min. ? max. ? unit ? v oh output high voltage i oh = -0.1 ma 1.7-1.95v 1.4 v v ol output low voltage i ol = 0.1 ma 1.7-1.95v 0.2 v v ih input high voltage (1) 1.7-1.95v 1.4 v dd + 0.2 v v il input low voltage (1) 1.7-1.95v C0.2 0.4 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a notes: 1. v ill (min.) = C1.0v ac (pulse width < 10ns). not 100% tested. v ihh (max.) = v dd + 1.0v ac (pulse width < 10ns). not 100% tested.
integrated silicon solution, inc. www.issi.com 5 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll ac ? test?conditions ? parameter ? 1.7v-1.95v ? 2.5v-3.6v ? ? ? ? ? ? ? (unit)? (unit) ? input pulse level 0.4v to v dd -0.2 0.4v to v dd -0.3v input rise and fall times 5 ns 5ns input and output timing v ref v ref and reference level output load see figures 1 and 2 see figures 1 and 2 ac ? test? loads figure?1 figure?2 ? ? 1.7v?-?1.95v?? 2.5v?-?3.6v ? r1(?) 3070 1029 r2(?) 3150 1728 v ref 0.9v 1.4v v tm 1.8v 2.8v capacitance (1) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. r1 5 pf including jig and scope r2 output vtm r1 30 pf including jig and scope r2 output vtm
6 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll 1.7v-1.95v ? power? supply? characteristics? (over operating range) symbol? parameter ? test ?conditions? ? ? ? max. ? unit ? ? ? ? ? ? ? 70ns i cc v dd dynamic operating v dd = max., com. 20 ma supply current i out = 0 ma, f = f max ind. 25 all inputs 0.4v auto. 30 or v dd C 0.2v i cc 1 operating supply v dd = max., cs1 = 0.2v com. 4 ma current we = v dd C 0.2v ind. 4 cs2 = v dd C 0.2v, f = 1 mhz auto. 10 i sb 1 ttl standby current v dd = max., com. 0.6 ma (ttl inputs) v in = v ih or v il ind. 0.6 cs1 = v ih , cs2 = v il , a uto . 1 f = 1 mh z ? ? or ulb control v dd = max., v in = v ih or v il cs1 = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v dd = max., com. 100 a current (cmos inputs) cs1 v dd C 0.2v, ind. 120 cs2 0.2v, auto. 150 v in v dd C 0.2v, or v in 0.2v, f = 0 ? ? or ulb control v dd = max., cs1 = v il , cs2=v ih v in v dd C 0.2v, or v in 0.2v, f = 0; ub / lb = v dd C 0.2v note:. 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
integrated silicon solution, inc. www.issi.com 7 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll 2.5v-3.6v ? power? supply? characteristics? (over operating range) symbol? parameter ? test ?conditions ? ? ? ? max. ? ? unit ? ? ? ? ? ? ? 55ns? i cc v dd dynamic operating v dd = max., com. 25 ma supply current i out = 0 ma, f = f max ind. 28 all inputs 0.4v auto. 35 or v dd C 0.3v typ. (2) 15 i cc 1 operating supply v dd = max., cs1 = 0.2v com. 5 ma current we = v dd C 0.2v ind. 5 cs2 = v dd C 0.2v, f = 1 mhz a uto . 10 i sb 1 ttl standby current v dd = max., com. 0.6 ma (ttl inputs) v in = v ih or v il ind. 0.6 cs1 = v ih , cs2 = v il , a uto . 1 f = 1 mh z ? ? or ulb control v dd = max., v in = v ih or v il cs1 = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v dd = max., com. 100 a current (cmos inputs) cs1 v dd C 0.2v, ind. 130 cs2 0.2v, auto. 150 v in v dd C 0.2v, or typ. (2) 75 v in 0.2v, f = 0 ? ? or ulb control v dd = max., cs1 = v il , cs2=v ih v in v dd C 0.2v, or v in 0.2v, f = 0; ub / lb = v dd C 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
8 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll data valid previous data valid t aa t oha t oha t rc d q0-d15 address ac ? waveforms read?cycle? no. ?1 (1,2)? (address controlled) (cs1 = oe = v il , cs2 = we = v ih , ub or lb = v il ) read?cycle?switching? characteristics (1) ? (over operating range) ? ??????????????????????????????????? 55?ns ? ??????????????????????????????????????70?ns ? ? symbol? parameter ? ? ? min. ? max. ? min. ? max. ? unit t rc read cycle time 55 70 ns t aa address access time 55 70 ns t oha output hold time 10 10 ns t a cs 1/ t a cs 2 cs1/ cs2 access time 55 70 ns t doe oe access time 25 35 ns t hzoe (2) oe to high-z output 20 25 ns t lzoe (2) oe to low-z output 5 5 ns t hzcs 1/ t hzcs 2 (2) cs1/cs2 to high-z output 0 20 0 25 ns t lzcs 1/ t lzcs 2 (2) cs1/ cs2 to low-z output 10 10 ns t ba lb, ub access time 55 70 ns t hzb lb, ub to high-z output 0 20 0 25 ns t lzb lb, ub to low-z output 0 0 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v dd -0.2v/0.4v to v dd -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 100 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. www.issi.com 9 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs1 address oe cs1 cs2 dout lb , ub t hzb t ba t lzb ac ? waveforms read?cycle? no. ?2 (1,3) (cs1, cs2, oe, and ub/lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1, ub, or lb = v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low transition.
10 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (cs1) [ (lb) = (ub) ] (we). ac ? waveforms write?cycle? no. ?1 (1,2) ? (cs1 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb, ub t pwb write?cycle?switching? characteristics (1,2) (over operating range) ? ?????????????????? 55?ns ? ?????????????????????????????????????70?ns ? symbol? parameter ? ??? min. ? max. ? ?? min. ? max. ? unit t wc write cycle time 55 70 ns t scs 1/ t scs 2 cs1/ cs2 to write end 45 60 ns t aw address setup time to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address setup time 0 0 ns t pwb lb, ub valid to end of write 45 60 ns t pwe (4) we pulse width 45 15,000 (5) 60 15,000 (5) ns t sd data setup to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe (3) we low to high-z output 20 30 ns t lzwe (3) we high to low-z output 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v dd -0.2v/0.4v to v dd -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 100 mv from steady-state voltage. not 100% tested. 4. t pwe > t hzwe + t sd when oe is low. 5. refer to avoidable timing and recommendations for clear defnition.
integrated silicon solution, inc. www.issi.com 11 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll write?cycle? no. ?2? (we controlled: oe is high during write cycle) write?cycle? no. ?3? (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din
12 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll write?cycle? no. ?4? (ub/lb controlled) data undefined t wc address 1 address 2 t wc high-z t pwb word 1 low word 2 t hd t sa t hzwe address cs1 ub, lb we d out d in oe data in valid t lzwe t sd t pwb data in valid t sd t hd t sa t ha t ha ub_cswr4.eps high cs2
integrated silicon solution, inc. www.issi.com 13 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll avoidable?timing?and?recommendations avoidable ? timing ? figure? 2a ? ? ? figure? 2b ? ? ? figure? 2c ? ? ? figure? 3a ? ?
14 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll avoidable?timing?and?recommendations notes: 1. psram uses dram cell which needs a refresh action periodically to retain the information. this refresh action is per - formed internally as part of a read cycle or when the device is not selected. a hidden refresh action has to be executed by the device at least once every 15 m s. 2. figure 2a shows a timing example in which consecutive read cycles occurs in intervals less than the trc spec while the device is selected for a period of 15 m s. this timing should be avoided because output data from these read cycles are not guaranteed to be valid due to violation of the trc spec. this timing also prohibits the device from performing a hidden re - fresh action properly. examples on how to avoid the timing in figure 2a are shown in figure 2b and 2c. 3. figure 3a shows a timing example in which a single write operation is maintained for a period greater than 15 m s. since a refresh action cannot be performed during a write operation, information stored in the device will not be retained if this timing occurs. a write operation is initiated when active low signals we, cs, ub and lb are enabled (logic low) but any one of these signals can be disabled (logic high) to complete the write operation. figure 3b is a timing example of using signal cs being disabled to complete the write operation. 4. since a refresh action cannot be performed during a write operation, consecutive write cycles occurring for a total period greater than 15 m s are not permitted. however, executing consecutive write cycles greater than 15m s is acceptable if either we, cs, or both ub and lb , are disabled (logic high) for a period of at least 5ns or higher and can be done once or multiple times. an example using cs signal is shown in figure 4 ? figure? 3b ? 15us ? address cs ? or ? ub ? & ? lb we ? ? figure? 4 ? ? ? ?
integrated silicon solution, inc. www.issi.com 15 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll is66wv51216dall industrial? range: ?-40c?to?+85c? voltage ? range: ?1.7v?to?1.95v? ? speed?(ns)? order ? part?no. ? package 70 is66wv51216dall-70tli tsop-ii, lead-free is66wv51216dall-70bli mini bga (6mm x 8mm), lead-free is66wv51216dbll industrial? range: ?-40c?to?+85c? voltage ? range: ?2.5v?to?3.6v? ? speed?(ns)? order ? part?no. ? package 55 is66wv51216dbll-55tli tsop-ii, lead-free is66wv51216dbll-55bli mini bga (6mm x 8mm), lead-free 70 is66wv51216dbll-70tli tsop-ii, lead-free is66wv51216dbll-70bli mini bga (6mm x 8mm), lead-free is67wv51216dbll automotive ?(a1)? range: ?-40c?to?+85c? voltage ? range: ?2.5v?to?3.6v? ? speed?(ns)? order ? part?no. ? package 55 is67wv51216dbll-55tla1 tsop-ii, lead-free is67wv51216dbll-55bla1 mini bga (6mm x 8mm), lead-free 70 is67wv51216dbll-70tla1 tsop-ii, lead-free is67wv51216dbll-70bla1 mini bga (6mm x 8mm), lead-free
16 integrated silicon solution, inc. www.issi.com rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline
integrated silicon solution, inc. www.issi.com 17 rev.? a 06/28/2011 is66wv51216dall is66/67wv51216dbll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline

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